THE COMPLETE PLL SOLUTION
TRU-050
Flexible Modular Solution
A Quartz Stabilized PLL
It's a phased-locked loop ASIC with a quartz stabilized VCXO!
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It will:
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design time
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jitter performance
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component count
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reliability
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board space
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It performs:
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- Clock recovery & data retiming
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In applications up to 65.536 Mb/s:
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- XDSL, Network communications
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- Digital audio/video, PBX systems
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What Does It Do?
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Vectron International's TRU-050 module is a user-configured, phase-locked loop
(PLL) solution designed to simplify a wide variety of clock recovery and data
retiming, frequency translation and clock smoothing applications. The device
features a phase-lock loop ASIC with a quartz stabilized VCXO for superior
stability and jitter performance. This highly integrated module provides
unsurpassed performance, reliability and quality. The proprietary ASIC device
includes a refined Phase Detector, a Loop Filter Op-Amp, a Loss of Signal Alarm
with Clock Return to Nominal feature, a VCXO circuit, and an optional 2n Output
Frequency Division circuit.
The ASIC and quartz resonator are housed in a
hermetic 16-pin DIL ceramic package with optional thru-hole or surface mount
leads. The VCXO frequency (OUT1) and division factor (OUT2) are factory set
in accordance with customer specifications. PLL response is optimized for
each application by the selection of three external passive components. Software
is available from Vectron to aid in loop filter component selection and loop
response modeling.
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Features:
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Benefits:
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PLL with quartz stabilized VCXO
Output jitter less than 20 ps
Loss of signal (LOS) alarm
Return to nominal clock upon LOS
Input data rates from 8 kb/s to 65.536 Mb/s
Surface mount option
Tri-state option
User defined PLL loop response
NRZ data compatible
Robust hermetic ceramic package
Single or +5.0V supply (+3.3V option available)
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Flexible modular solution
Reduce design time
Increase circuit reliability
Less board space
Reduces component count
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Electrical Characteristics
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Parameter
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Symbol
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Min
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Max
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Unit
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Input NRZ Data Rates
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DATAIN
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0.008
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65.536
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MHz
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Input RZ Data and Clock Rates1
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DATAIN
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0.016
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32.768
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MHz
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Nominal Output Frequency:
Output 1
Output 22
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OUT1
OUT2
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14.0
0.05
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65.536
32.768
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MHz
MHz
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Supply Voltage
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VDD
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4.5
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5.5
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V
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Supply Current (VDD=4.5 V)
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IDD
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25
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60
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mA
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Output Voltage Levels (VDD=4.5 V):
Output Logic High3
Output Logic Low3
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VOH
VOL
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2.5
-
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-
0.5
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V
V
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Transition Times3:
Rise Time (0.5 V to 2.5 V)
Fall Time (2.5 V to 0.5 V)
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tR
tF
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0.5
0.5
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5
5
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ns
ns
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Symmetry or Duty Cycle4:
Output 1
Output 22
Recovered Clock
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SYM1
SYM2
RCLK
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40
45
40
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60
55
60
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%
%
%
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Input Data:
Input Logic High3
Input Logic Low3
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VIH
VIL
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2.0
-
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0.8
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V
V
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Control Voltage Bandwidth (-3 dB, VC=2.50 V)
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BW
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50
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kHz
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Sensitivity @ VC=VO
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 F/VC
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See Figure 4.
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ppm/V
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Loss of Signal Indication5:
Output Logic High3
Output Logic Low3
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LOS
VOH
VOL
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2.5
-
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0.5
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V
V
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Nominal Output Frequency on Loss of Signal:
Output 1
Output 2
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OUT1
OUT2
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-75 ppm
-75 ppm
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75 ppm
75 ppm
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ppm from fo1
ppm from fo2
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Phase Detector Gain
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KD
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-0.53 x Data Density
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rad/V
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1. For input RZ data, Manchester encoded data, and input clock recovery applications, the output clock must run at two times the input rate to ensure that the input is clocked correctly. Since the output clock has a maximum frequency of 52.0 MHz, these inputs are limited to a maximum rate of 26 MHz.
2. OUT2 is a binary submultiple of OUT1, as specified in the device code shown in Figure 6. OUT2 may also be disabled.
3. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five-gate MTTL load and operating conditions under which these parameters are specified and tested.
4. Symmetry is the ON TIME/PERIOD in percent with VS=1.4 V for TTL, per Figure 2.
5. A loss of signal (LOS) indicator is set to a logic high if no transitions are detected at DATAIN after 256 clock cycles. As soon as a transition occurs at DATAIN, LOS is set to a logic low.
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Absolute Pull
Absolute pull range (APR) is specified by the fourth character of the product code.
The APR is the minimum guaranteed frequency shift from FO over variations
in temperature, aging, power supply, and load. Both frequency and environment limit
the specified APR. The total pull range for the VCXO contained in the TRU050 is
typically between 200 ppm and 400 ppm.
A 50 ppm APR TRU050 fully tracks a 50 ppm source oscillator or any other 50 ppm reference
over the operating temperature range, life of the product, power supply and measurement
variations.
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Parameter
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Symbol
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Min
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Max
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Unit
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Absolute Frequency Pull Range
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APR
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-APR
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APR
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ppm from FO
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Outline Diagram
Thru-Hole
Surface Mount
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Pin Information
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Pin#
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Symbol
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Type
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Function
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1
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VC
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Control voltage input to internal voltage-controllable crystal oscillator (VCXO).
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2
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OPN
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Negative input terminal to internal operational amplifier.
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3
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OPOUT
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O
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Output terminal of internal operational amplifier.
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4
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OPP
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Positive input terminal to internal operational amplifier.
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5
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LOSIN
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With LOSIN set to a logic high, the external input to the VCXO (VC)
is disabled and the VCXO returns to its nominal center frequency. With LOSIN
set to logic low, the external input to the VCXO is enabled. The LOSIN input
has an internal pull-down resistor.
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6
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PHO
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O
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Output signal produced by phase detector and used as VC at Pin1.
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7
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DATAIN
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Input data stream to phase detector (TTL switching thresholds).
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8
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GND
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Circuit and cover ground.
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9
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CLKIN
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Input clock signal to phase detector (TTL switching thresholds)..
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10
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LOS
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O
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Loss of signal indicator is set to a logic high if no transitions are detected at
DATAIN after 256 clock cycles. As soon as a transition occurs at DATAIN, LOS is
set to a logic low.
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11
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RCLK
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O
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TTL compatible recovered clock.
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12
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RDATA
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O
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TTL compatible recovered data stream.
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13
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OUT2
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O
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Divided version of internal VCXO output clock (TTL).
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14
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HIZ
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When set to a logic low, output pins OUT1, OUT2, RCLK, and RDATA buffers are set to high-impedance state. When set to a logic high or no connect, the device functions and output pins OUT1, OUT2, RCLK, and RDATA are active. This input has an internal pull-up resistor.
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15
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OUT1
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O
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Output clock of internal VCXO (TTL).
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16
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VDD
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5 V ± 10% supply voltage. (3.3 V option available)
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Standard Frequencies* (MHz) using OUT 1
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12.032
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12.288
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12.624
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13.824
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16.000
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16.128
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16.384
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16.777
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16.896
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17.920
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18.432
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18.936
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19.440
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20.000
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20.480
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22.1184
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22.579
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24.576
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24.704
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25.000
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25.248
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28.000
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30.720
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32.000
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32.768
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33.330
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34.368
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38.880
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40.000
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40.960
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41.2416
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41.943
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44.736
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47.457
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49.152
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49.408
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50.000
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51.840
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65.536
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Standard Frequencies* (MHz) using OUT 2
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1.000
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1.024
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1.544
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2.048
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3.088
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3.240
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4.032
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4.096
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4.1925
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4.224
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5.592
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6.016
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6.144
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6.312
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6.480
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6.912
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7.680
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8.000
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8.192
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8.448
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8.960
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9.468
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9.720
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10.000
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10.240
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11.0592
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12.352
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12.500
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12.960
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14.000
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16.000
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16.384
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16.665
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19.440
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20.000
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20.6208
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20.9715
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22.368
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23.7285
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24.576
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24.704
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25.920
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32.768
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* Other frequencies available upon request.
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